A New Method for Mitigation SEU Errors in Three-Dimensional FPGAs
نویسندگان
چکیده
Now a day's one of the most crucial issues in the field of FPGAGs, especially in SRAM FPGAs is single event upsets. One of the most effective methods to decrease these errors is using three dimensional FPGAs. This paper presents evaluation and mitigation of SEU cost on six layers three-dimensional (3D) FPGAs. The evaluation results show that SUE rate decrease about 67% on six layers 3D FPGAs. We also estimate the SEU cost improvement due to changing the place of 6 layers on 3D FPGAs, and it shows 28% improvements. However because of the importance of Trough Silicon Vias (TSVs) on delay estimation, we tried to make a trade-off between total TSV length and SEU costs.
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